logobossness

REVELPROG-IS is a professional tool for serial memory programming. It supports wide range of EEPROM, FLASH and FRAM devices with I2C, SPI, 1-Wire and MICROWIRE (uWire) protocols powered with 1.0V - 5.0V voltage levels. It has integrated ZIF socket (for THT devices) and SOIC socket (for SMD devices). It has also connector for in-circuit serial programming (ICSP) with buffered I/O. Due to USB 2.0 interface memory operations are incredibly fast.

• Eeprom Programmer Software

Serial EEPROM Programmer Here is a simple serial (I2C) EEPROM programmer for the PC parallel port. I built it to program 24XX devices, but it can, in principle at least, talk to any I2C device with a suitable adapter or fly-lead, it implements a complete I2C bus interface. His follow-up to “Using an EEPROM to replace combinational logic” is a one-hour marathon entitled “Build an EEPROM Arduino programmer’”. It uses an Arduino, two 74HC595 shift registers and a 28C16 EEPROM to take the slog out of manual programming.

Description

Application:

Serial memory programming in:

• car electronics & automotive (reprogramming modules, radio-code, immobilizers, gps navigations, mileage correction and other modules with serial EEPROM and/or FLASH memories),
• computer and notebook service (data recovery, reflashing, upgrading and programming BIOS chips in motherboards, copier & fax machines, printers, hdd & ssd sata drives etc. ),
• network service (programming and cloning optical and ethernet SFP & SFP+ modules),
• RTV/AGD maintaining or repairing (TV, digital cameras, tv tuners etc.),
• and many other devices equipped with serial IIC / SPI / Microwire EEPROM and SPI FLASH chips.

Main features:

• reading / writing / erasing functions with user-friendly application interface,
• supported binary files (*.bin, *.rom, *.epp etc.) and Intel-Hex (*.hex) with possibility to load file to the buffer, edit it, calculate checksums, export changes as patterns, swap-bytes, compare with chip etc.),
• programming in socket or in external circuit (without unsoldering the chip - in system programming ISP),
• the target application device can be either powered by REVELPROG (possibility to change VPP and logic levels: 1.0V / 1.5V / 1.8V / 2.5V / 2.8V / 3.3V / 5.0V) or powered by an application with external power supply (1.0 – 5.5V),
• build in additional protection: buffered I/O pins internal connected only during programming + short circuit and overload protection (reduces the risk of damaging parts due to connection mistake),
• all I/O internal-connected only during programming,
• additional useful tools such as: user patterns, script programming (i2c & spi bus pirate), checksums, auto backups, file comparing (DiffChecker) etc.
• integrated sockets (ZIF + SOIC) with auto adaptive I/O pins reduces requirement of additional adapters,
• short programming time , e.g. WINBOND W25Q80BV (8Mb): read 0.9s (8,4Mb/s), write 3.3s (2,4Mb/s), MICRON N25Q128A (128Mb): read 12.8s (10Mb/s), write 37.6s (3,4Mb/s), please check video programming examples
• software and firmware upgrades are freely available for all users on the Internet.

Technical data:

• compatible protocols: IIC (I2C), SPI, 1-WIRE and MICROWIRE (uWire),
• supported device with 1.0V – 5.0V power supply,
• power supply and communication via USB 2.0 (hardware level, bulk transfer),
• programming with external power supply (1.0 - 5.5V),
• programming with internal power supply (1.0 - 5.0V, Imax = 100mA),
• operation speed (read/write) up to 10Mbit/s,
• ZIF-32 + SOIC-8 (150mil) integrated sockets,
• connector for in-circuit serial programming (ICSP) with buffered I/O,
• auto adaptive I/O pins connected only for programming time (Hi-Z in IDLE state),
• all I/O connected only for programming time (Hi-Z in IDLE state),
• short circuit and overload protection,
• software compatible with Windows XP, Vista, 7, 8 and 10 (32 and 64-bit),
• device designed & manufactured in EU, made in Poland.

Device list:

Please go to 'Supported Chips' tab at the top.

Software:

Software is compatible with MS Windows XP, Vista, 7, 8 and 10 (32 and 64-bit).

Application interface is user-friendly. It has all buffer editor functions and also additonal features commonly used in car electronics and IT, such as swap-bytes, calculate checksums, saving changes to external files (as patterns), custom scripts maker for I2C/SPI (bus pirate), SFP editor etc. All main functions can be run directly from shortcut icons:

Software can be downloaded free of charge directly from our webpage (click 'software' tab or go to 'technical support' page).

Updates:

Updates are free of charge. Update consist of software update (pc application) and firmware update (software inside the device). Latest software can be downloaded directly from our webpage. You will be informed by the software about possible updates after connecting out of date device.

User Manual:

User Manual can be downloaded from 'manuals' tab at the top of the page. It can be downloaded also from 'technical support' page.

Supported Chips

The following list details the family of supported devices with selected examples of supported memories. Most chips have the same programming procedures – programmer supports more devices than the examples given in the list.

Tip: please click CTRL + F in your browser to quick find

EEPROM I2C 24… series

EEPROM SPI 25… series

EEPROM SPI 35… series

EEPROM SPI 95… series

EEPROM MICROWIRE 93… series

Compatible both addressing modes (8- and 16-bit)

EEPROM SPI 90… series

EEPROM 1-wire devices

FLASH SPI 25.. series

Supports low-voltage serial flash memories (1.2V, 1.8V, 2.5V) and standard (3.3V)

FLASH SPI 26.. series

Supports low-voltage serial flash memories (1.8V) and standard (3.3V)

DATA FLASH SPI 45.. series

FLASH SPI NAND

Metex me 11 manual. Supports low-voltage serial flash memories (1.8V) and standard (3.3V)

F-RAM I2C 24… series

F-RAM SPI 25… series

SFP / SFP+ optical & ethernet modules

Please note that there is SFP adapter required with external power supply!

Gallery

Programmer Gallery

Software Gallery

Videos

Programming example of EEPROM in DIP-8 and SOIC-8 sockets

Programming example of FLASH (64Mbit) in SOIC-8 200mil adapter

Low-voltage FLASH SPI programming in HDD board without desoldering the chip (ISP - in-circuit serial programming with SOIC clip)

Instrument cluster in-circuit serial programming ICSP (in system programming with SOIC-8 clip without desoldering the chip)

SFP optical transceivers module programming with SFP adapter

More movies

More videos you can find on REVELTRONICS' youtube channel.

Set

Set includes:

• REVELPROG IS serial device programmer,
• Tape for ICSP programming (~30cm),
• USB 2.0 cable.

Download:

• User manual in PDF,
• REVELPROG-IS Software.

REVELPROG-IS is available at REVELTRONICS's store.

Manuals

User Manual:

Software

Software download:

Latest release:

• REVELPROG IS v1.8.1 EN (windows installer) - NEW

• REVELPROG IS v1.8.1 EN (file archive .zip) - NEW

Previous releases:

• REVELPROG IS v1.8.0 EN (windows installer)

• REVELPROG IS v1.7.1 EN (windows installer)

Need older version? Check archived versions.

Change log (few last releases):

Reviews

REVELPROG-IS Reviews

Eeprom Programmer Software

EEPROM (also E²PROM) stands for electrically erasable programmable read-only memory and is a type of non-volatile memory used in computers, integrated in microcontrollers for smart cards and remote keyless systems, and other electronic devices to store relatively small amounts of data but allowing individual bytes to be erased and reprogrammed.

EEPROMs are organized as arrays of floating-gate transistors. EEPROMs can be programmed and erased in-circuit, by applying special programming signals. Originally, EEPROMs were limited to single byte operations, which made them slower, but modern EEPROMs allow multi-byte page operations. An EEPROM has a limited life for erasing and reprogramming, now reaching a million operations in modern EEPROMs. In an EEPROM that is frequently reprogrammed while the computer is in use, the life of the EEPROM is an important design consideration.

Flash memory is a type of EEPROM designed for high speed and high density, at the expense of large erase blocks (typically 512 bytes or larger) and limited number of write cycles (often 10,000). There is no clear boundary dividing the two, but the term 'EEPROM' is generally used to describe non-volatile memory with small erase blocks (as small as one byte) and a long lifetime (typically 1,000,000 cycles). Many microcontrollers include both: flash memory for the firmware, and a small EEPROM for parameters and history.

• 5Electrical interface
• 7Related types

History[edit]

In early 1970s, some studies, inventions, and development for electrically re-programmable non-volatile memories were performed by various companies and organizations.In 1971, the earliest research report was presented at the 3rd Conference on Solid State Devices, Tokyo in Japan by Yasuo Tarui, Yutaka Hayashi, and Kiyoko Nagai at Electrotechnical Laboratory; a Japanese national research institute.^[1]They fabricated an EEPROM device in 1972,^[2] and continued this study for more than 10 years.^[3]These papers have been repeatedly cited by later papers and patents.^[4][5]

One of their research includes MONOS (metal-oxide-nitride-oxide-semiconductor) technology,^[6]which is used Renesas Electronics' flash memory integrated in single-chip microcontrollers.^[7][8][9]

In 1972, a type of electrically re-programmable non-volatile memory was invented by Fujio Masuoka at Toshiba, who is also known as the inventor of flash memory.^[10]Most of major semiconductor manufactures, such asToshiba,^[10][4]Sanyo (later, ON Semiconductor),^[11]IBM,^[12]Intel,^[13][14]NEC (later, Renesas Electronics),^[15]Philips (later, NXP Semiconductors),^[16]Siemens (later, Infineon Technologies),^[17]Honeywell (later, Atmel),^[18]Texas Instruments,^[19]studied, invented, and manufactured some electrically re-programmable non-volatile devices until 1977.

The theoretical basis of these devices is Avalanchehot-carrier injection. But in general, programmable memories, including EPROM, of early 1970s had reliability problems such as the data retention periods and the number of erase/write cycle endurance.^[20]

In 1975, NEC's semiconductor operations unit, later NEC Electronics, currently Renesas Electronics, applied the trademark name EEPROM® to Japan Patent Office.^[21][22]In 1978, this trademark right is granted and registered as No.1,342,184 in Japan, and still survives as of March 2018.

In February 1977, Eliyahou Harari at Hughes Aircraft Company invented a new EEPROM technology using Fowler-Nordheim tunnelling through a thin silicon dioxide layer between the floating-gate and the wafer. Hughes went on to produce this new EEPROM devices.^[23]But this patent^[24]cited NEC's EEPROM® invention.^[15]

In May 1977, some important research result was disclosed by Fairchild and Siemens. They used SONOS (polysilicon-oxynitride-nitride-oxide-silicon) structure with thickness of silicon dioxide less than 30 Å, and SIMOS (stacked-gate injectionMOS) structure, respectively, for using Fowler-Nordheim tunnellinghot-carrier injection.^[25][26]

Around 1976 to 1978, Intel's team, including George Perlegos, made some inventions to improve this tunneling E²PROM technology.^[27][28]In 1978, they developed a 16K (2K word × 8) bit Intel 2816 device with a thin silicon dioxide layer, which was less than 200 Å.^[29]In 1980. this structure was publicly introduced as FLOTOX; floating gatetunneloxide.^[30]The FLOTOX structure improved reliability of erase/write cycles per byte up to 10,000 times.^[31]But this device required additional 20–22V V_PP bias voltage supply for byte erase, except for 5V read operations.^[32]:5-86In 1981, Perlegos and 2 other members left Intel to form Seeq Technology,^[33]which used on-device charge pumps to supply the high voltages necessary for programming E²PROMs.In 1984, Perlogos left Seeq Technology to found Atmel, then Seeq Technology was acquired by Atmel.^[34][35]

Theoretical basis of FLOTOX structure[edit]

As is described in former section, old EEPROMs are based on Avalanche breakdown-based hot-carrier injection with high reverse breakdown voltage. But FLOTOX's theoretical basis is Fowler–Nordheim tunnelinghot-carrier injection through a thin silicon dioxide layer between the floating-gate and the wafer. In other words, it uses tunnel junction.^[36]

Theoretical basis of the physical phenomenon itself is the same as today's flash memory. But each FLOTOX structure is in conjunction with another read-control transistor because the floating gate itself is just programming and erasing one data bit.^[37]

Intel's FLOTOX device structure improved EEPROM's reliability, in other words, the write and erase cycles endurance, and the data retention period. A material of study for single event effect about FLOTOX is available.^[38]

Today, detailed academical explanation of FLOTOX device structure can be found in various materials.^[39][40][41]

Today's EEPROM structure[edit]

Nowadays, EEPROM is used for embedded microcontrollers as well as standard EEPROM products. EEPROM still requires 2 transistors structure per bit to erase a dedicated byte in the memory, while flash memory has 1 transistor per bit to erase a region of the memory.^{[42]:245, PDF:2}

Security protections[edit]

Because EEPROM technology is used for some security gadgets, such as credit card, SIM card, key-less entry, etc., some devices have security protection mechanisms.^[42][43]

Electrical interface[edit]

EEPROM devices use a serial or parallel interface for data input/output.

Serial bus devices[edit]

The common serial interfaces are SPI, I²C, Microwire, UNI/O, and 1-Wire. These use from 1 to 4 device pins and allow devices to use packages with 8-pins or less.

A typical EEPROM serial protocol consists of three phases: OP-Code Phase, Address Phase and Data Phase. The OP-Code is usually the first 8-bits input to the serial input pin of the EEPROM device (or with most I²C devices, is implicit); followed by 8 to 24 bits of addressing depending on the depth of the device, then the read or write data.

Each EEPROM device typically has its own set of OP-Code instructions mapped to different functions. Common operations on SPI EEPROM devices are:

• Write Enable (WRENAL)
• Write Disable (WRDI)
• Read Status Register (RDSR)
• Write Status Register (WRSR)
• Read Data (READ)
• Write Data (WRITE)

Other operations supported by some EEPROM devices are:

• Program
• Sector Erase
• Chip Erase commands

Parallel bus devices[edit]

Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide enough to cover the complete memory. Most devices have chip select and write protect pins. Some microcontrollers also have integrated parallel EEPROM.

Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count (28 pins or more) and have been decreasing in popularity in favor of serial EEPROM or flash.

Other devices[edit]

EEPROM memory is used to enable features in other types of products that are not strictly memory products. Products such as real-time clocks, digital potentiometers, digital temperature sensors, among others, may have small amounts of EEPROM to store calibration information or other data that needs to be available in the event of power loss.It was also used on video game cartridges to save game progress and configurations, before the usage of external and internal flash memories.

Failure modes[edit]

There are two limitations of stored information; endurance, and data retention.

During rewrites, the gate oxide in the floating-gate transistors gradually accumulates trapped electrons. The electric field of the trapped electrons adds to the electrons in the floating gate, lowering the window between threshold voltages for zeros vs ones. After sufficient number of rewrite cycles, the difference becomes too small to be recognizable, the cell is stuck in programmed state, and endurance failure occurs. The manufacturers usually specify the maximum number of rewrites being 1 million or more.^[44]

During storage, the electrons injected into the floating gate may drift through the insulator, especially at increased temperature, and cause charge loss, reverting the cell into erased state. The manufacturers usually guarantee data retention of 10 years or more.^[45]

Related types[edit]

Flash memory is a later form of EEPROM. In the industry, there is a convention to reserve the term EEPROM to byte-wise erasable memories compared to block-wise erasable flash memories. EEPROM occupies more die area than flash memory for the same capacity, because each cell usually needs a read, a write, and an erase transistor, while flash memory erase circuits are shared by large blocks of cells (often 512×8).

Newer non-volatile memory technologies such as FeRAM and MRAM are slowly replacing EEPROMs in some applications, but are expected to remain a small fraction of the EEPROM market for the foreseeable future.

Comparison with EPROM and EEPROM/flash[edit]

The difference between EPROM and EEPROM lies in the way that the memory programs and erases. EEPROM can be programmed and erased electrically using field electron emission (more commonly known in the industry as 'Fowler–Nordheim tunneling').

EPROMs can't be erased electrically and are programmed via hot carrier injection onto the floating gate. Erase is via an ultraviolet light source, although in practice many EPROMs are encapsulated in plastic that is opaque to UV light, making them 'one-time programmable'.

Most NOR flash memory is a hybrid style—programming is through hot carrier injection and erase is through Fowler–Nordheim tunneling.

In popular culture[edit]

The Stanford Graduate Students in Electrical Engineering (GSEE) has annually hosted a dance (i.e. prom) called EEPROM^[46] since 2012.

See also[edit]

• Intel HEX – file format
• SREC – file format

References[edit]

1. ^Tarui, Yasuo; Hayashi, Yutaka; Nagai, Kiyoko (1971-09-01). 'Proposal of electrically reprogrammable non-volatile semiconductor memory'. Proceedings of the 3rd Conference on Solid State Devices, Tokyo. The Japan Society of Applied Physics: 155–162.
2. ^Tarui, Y.; Hayashi, Y.; Nagai, K. (1972). 'Electrically reprogrammable nonvolatile semiconductor memory'. IEEE Journal of Solid-State Circuits. 7 (5): 369–375. Bibcode:1972IJSSC..7.369T. doi:10.1109/JSSC.1972.1052895. ISSN0018-9200.
3. ^Tarui, Yasuo; Nagai, Kiyoko; Hayashi, Yutaka (1974-07-19). 'Nonvolatile Semiconductor Memory'(PDF). Oyobuturi. 43 (10): 990–1002. doi:10.11470/oubutsu1932.43.990. ISSN2188-2290. Archived(PDF) from the original on 2018-03-12.
4. ^ ^abIizuka, H.; Masuoka, F.; Sato, Tai; Ishikawa, M. (1976). 'Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure'. IEEE Transactions on Electron Devices. 23 (4): 379–387. Bibcode:1976ITED..23.379I. doi:10.1109/T-ED.1976.18415. ISSN0018-9383.
5. ^Rossler, B. (1977). 'Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell'. IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED..24.606R. doi:10.1109/T-ED.1977.18788. ISSN0018-9383.
6. ^Suzuki, E.; Hiraishi, H.; Ishii, K.; Hayashi, Y. (1983). 'A low-voltage alterable EEPROM with metal—oxide-nitride—oxide—semiconductor (MONOS) structures'. IEEE Transactions on Electron Devices. 30 (2): 122–128. Bibcode:1983ITED..30.122S. doi:10.1109/T-ED.1983.21085. ISSN0018-9383.
7. ^XTECH, NIKKEI. 'Renesas Embeds 40nm Flash Memory on Chip'. NIKKEI XTECH. Archived from the original on 2018-03-13.
8. ^'Renesas Electronics Develops 90 nm One-Transistor MONOS Flash Memory Technology to Accelerate Intelligence in Automotive Control Systems'. Business Wire. 2016-01-03. Archived from the original on 2018-03-13.
9. ^Taito, Y.; Kono, T.; Nakano, M.; Saito, T.; Ito, T.; Noguchi, K.; Hidaka, H.; Yamauchi, T. (2015). 'A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170circ$ C'. IEEE Journal of Solid-State Circuits. 51 (1): 213–221. Bibcode:2016IJSSC.51.213. doi:10.1109/JSSC.2015.2467186. ISSN0018-9200. Archived from the original on 2018-05-03.
10. ^ ^abMasuoka, Fujio (31 August 1972). 'Avalanche injection type mos memory'.
11. ^Rai, Yasuki; Sasami, Terutoshi; Hasegawa, Yuzuru; Okazoe, Masaru (1973-05-18). 'Electrically reprogrammable nonvolatile floating gate semi-conductor memory device and method of operation'. Archived from the original on 2018-05-03.
12. ^Abbas, Shakir A.; Barile, Conrad A.; Lane, Ralph D.; Liu., Peter T (1973-03-16). 'US3836992A; Electrically erasable floating gate fet memory cell'. pdfpiw.uspto.gov. United States Patent and Trademark Office. Archived from the original on 2018-03-09.
13. ^Frohman, Bentchkowsky D (19 October 1973). 'Electrically alterable floating gate device and method for altering same'.
14. ^Chou, Sunlin (26 February 1973). 'Erasable floating gate device'.
15. ^ ^abOhya, Shuichi; Kikuchi, Masanori (1974-12-27). 'Non-volatile semiconductor memory device'.
16. ^Verwey, J. F.; Kramer, R. P. (1974). 'Atmos—An electrically reprogrammable read-only memory device'. IEEE Transactions on Electron Devices. 21 (10): 631–636. Bibcode:1974ITED..21.631V. doi:10.1109/T-ED.1974.17981. ISSN0018-9383.
17. ^B., Roessler; R. G., Mueller (1975). 'Erasable and electrically reprogrammable read-only memory using the N-channel SIMOS one-transistor cell'. Siemens Forschungs und Entwicklungsberichte. 4 (6): 345–351. Bibcode:1975SiFoE..4.345R.
18. ^Jack, S; Huang, T. (8 September 1975). 'Semiconductor memory cell'.
19. ^Gosney, W. M. (1977). 'DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology'. IEEE Transactions on Electron Devices. 24 (5): 594–599. Bibcode:1977ITED..24.594G. doi:10.1109/T-ED.1977.18786. ISSN0018-9383.
20. ^Moskowitz, Sanford L. (2016). 'reliability%20problems'+EPROM+1970s Advanced Materials Innovation: Managing Global Technology in the 21st century. John Wiley & Sons. ISBN9781118986097.
21. ^'EEPROM'. TMview. Archived from the original on 2018-03-10.
22. ^'Reg. No.1342184 – LIVE – REGISTRATION – Issued and Active'.
23. ^'Archived copy'(PDF). Archived(PDF) from the original on 2015-02-07. Retrieved 2015-02-05.CS1 maint: Archived copy as title (link)
24. ^Harari, Eliyahou (22 February 1977). 'Electrically erasable non-volatile semiconductor memory'. Archived from the original on 3 May 2018.
25. ^Chen, P. C. Y. (May 1977). 'Threshold-alterable Si-gate MOS devices'. IEEE Transactions on Electron Devices. 24 (5): 584–586. Bibcode:1977ITED..24.584C. doi:10.1109/T-ED.1977.18783. ISSN0018-9383.
26. ^Rossler, B. (May 1977). 'Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell'. IEEE Transactions on Electron Devices. 24 (5): 606–610. Bibcode:1977ITED..24.606R. doi:10.1109/T-ED.1977.18788. ISSN0018-9383.
27. ^Simko, Richard T. (17 March 1977). 'Electrically programmable and electrically erasable MOS memory cell'.
28. ^Frohman-Bentchkowsky, Dov; Mar, Jerry; Perlegos, George; Johnson, William S. (15 December 1978). 'Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same'.
29. ^Dummer, G. W. A. (2013). Electronic Inventions and Discoveries: Electronics from Its Earliest Beginnings to the Present Day. Elsevier. ISBN9781483145211.
30. ^Johnson, W.; Perlegos, G.; Renninger, A.; Kuhn, G.; Ranganath, T. (1980). 'A 16Kb electrically erasable nonvolatile memory'. 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXIII: 152–153. doi:10.1109/ISSCC.1980.1156030.
31. ^Euzent, B.; Boruta, N.; Lee, J.; Jenq, C. (1981). 'Reliability Aspects of a Floating Gate E2 PROM'. 19th International Reliability Physics Symposium: 11–16. doi:10.1109/IRPS.1981.362965. Archived from the original on 2018-03-13.
    The Intel 2816 uses the FLOTOX structure, which has been discussed in detail in the literaturel. Basically, it uses an oxide of less than 200A thick between the floating polysilicon gate and the N+ region as shown in Figure 1.
32. ^2816A-2 PDF Datasheet - Intel Corporation - Datasheets360.com. Intel. October 1983.
33. ^'Seeq Technology » AntiqueTech'. Archived from the original on 2014-10-02.
34. ^Rostky, George (July 2, 2002). 'Remembering the PROM knights of Intel'. EE Times. Archived from the original on September 29, 2007. Retrieved 2007-02-08.
35. ^Atmel AT28C16 datasheet(PDF) (0540B ed.). October 1998. Archived(PDF) from the original on 2017-08-29.
36. ^Gutmann, Peter (2001-08-15). 'Data Remanence in Semiconductor Devices'. 10th USENIX SECURITY SYMPOSIUM. IBM T.J.Watson Research Center: 39–54. Archived from the original on 2016-10-12.
37. ^Janwadkar, Sudhanshu (2017-10-24). 'Fabrication of Floating Gate MOS (FLOTOX)'. www.slideshare.net.
38. ^Koga, R.; Tran, V.; George, J.; Crawford, K.; Crain, S.; Zakrzewski, M.; Yu, P. 'SEE Sensitivities of Selected Advanced Flash and First-In-First-Out Memories'(PDF). The Aerospace Corporation. Archived(PDF) from the original on 2018-03-14.
39. ^Fuller, Dr. Lynn (2012-02-22). CMOS Process Variations EEPROM Fabrication Technology. Microelectronic Engineering, Rochester Institute of Technology.
40. ^Groeseneken, G.; Maes, H.E.; VanHoudt, J.; Witters, J.S. Basics of Nonvolatile Semiconductor Memory Devices. CiteSeerX10.1.1.111.9431.
41. ^Bergemont, Albert; Chi, Min-Hwa (1997-05-05). 'US Patent 5856222: Method of fabricating a high density EEPROM cell'. patents.google.com. National Semiconductor Corp.
42. ^ ^abSkorobogatov, Sergei (2017). How Microprobing Can Attack Encrypted Memory(PDF). 2017 Euromicro Conference on Digital System Design (DSD). Vienna. pp. 244–251. doi:10.1109/DSD.2017.69. ISBN978-1-5386-2146-2.
43. ^'Breaking copy protection in microcontrollers'. www.cl.cam.ac.uk. Archived from the original on 2017-10-22.
44. ^'Frequently Asked Questions -ROHM Semiconductor'. Archived from the original on 2011-02-19.
45. ^System Integration - From Transistor Design to Large Scale Integrated Circuits
46. ^'Stanford Graduate Students in Electrical Engineering (GSEE) - Facebook'. Archived from the original on 2017-12-07.

External links[edit]